RTC clock synchronization buffer driver delay chip

The NB3F8L3005C is a 2:1:5 clock/data fanout buffer, supported on one 3.3 V / 2.5 V core VDD and two 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOx flexible power supplies (less than or equal to VDD) run. A mux must be selected between a crystal input or a differential/SE clock/data input. Differential inputs accept LVPECL, LVDS, HCSL, or SSTL and single-ended levels. According to Table 3, the MUX control line SEL will select CLK/CLK or crystal input pin. When the clock input is selected, the crystal input is disabled. According to Table 4, if the output enable pin OE is low, the synchronization is forced to a high impedance state (Hi?Z). Outputs include five single-ended LVCMOS outputs.