RTC clock synchronization buffer driver delay chip

The NB3L208K is a differential 1:8 clock fanout buffer with high-speed current steering (HCSL) outputs. The inputs accept differential LVPECL, LVDS, and HCSL signals directly. Single-ended LVPECL, HCSL, LVCMOS or LVTTL levels are accepted with an appropriate external Vth reference supply, see Figures 4 and 6. The input signal is converted to HCSL, capable of running eight identical versions up to 350 MHz. The NB3L208K is optimized for ultra-low phase disturbance, propagation delay variation, and low output-to-output skew, and complies with the DB800H standard. Thus, system designers can take advantage of the performance of the NB3L208K to distribute low-skew clocks in backside pads or motherboards, making it suitable for clock and data distribution applications such as PCI Express, FBDIMMs, networking, mobile computing, Gigabit Ethernet, and more. The output drive current is set by connecting a 475 resistor from IREF (pin 27) to GND, as shown in Figure 11. The output can also be interfaced to an LVDS receiver when terminated, as shown in Figure 12.