RTC clock synchronization buffer driver delay chip

The MC100LVEL34 is a low-skew divide-by-2, 4, and 8 clock generation chip specifically designed for low-skew clock generation applications. The internal dividers are synchronized with each other so that the common output edges are all precisely aligned. Only the VBB pin, the internally generated supply voltage, is provided for this device. For the single-ended input case, the unused differential input is tied to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC with 0.01 μF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. The common enable (ENbar) is synchronous, so the internal divider is only enabled/disabled when the internal clock is already in a low state. This avoids short clock pulses on the internal clock when the device is enabled/disabled, which can happen with asynchronous control. Internal runt pulses can cause loss of synchronization between internal divider stages. The internal enable flip-flops are clocked on the falling edge of the input clock, therefore, all relevant specification limits are referenced to the negative edge of the clock input. On start-up, internal flip-flops are brought to a random state; a master clock reset (MR) input enables synchronization between internal dividers and between multiple LVEL34s in the system.