Memory chip

The CAT24C512 is an EEPROM serial 512-Kb I2C internally organized as 65,536 words of 8 bits each. It has a 128-byte page write cache and supports standard (100 kHz), fast (400 kHz), and ultra-fast (1 MHz) I2C protocols. Write operations can be disabled by pulling the WP pin high (this protects the entire memory). External address pins make it possible to place up to eight CAT24C512 devices on the same bus. On-chip ECC (Error Correction Code) makes the device suitable for high-reliability applications.

1kb

The CAV25256 is an EEPROM serial 256-Kb SPI - automotive grade device internally organized as 32Kx8 bits. It has a 64-byte write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a chip select (CS) input. Additionally, the required bus signals are the clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input can be used to suspend any serial communication with the CAV25256 device. The device features software and hardware write protection, including partial and full array protection. On-chip ECC (Error Correction Code) makes the device suitable for high-reliability applications.